Method of forward error correction

ABSTRACT

An iterative method of correcting errors in a data block. Bad bytes are first identified using information derived from an 8 B/10 B decoding of the data block. Within each identified bad byte, suspect bits are subsequently identified using information derived from parity decoding of a row of the data block. Each suspect bit is then classified as either a confirmed error bit or an unconfirmed error bit using information derived from parity decoding of a column of the data block in which the suspect bit is located. Confirmed error bits are then corrected, the parity bits corresponding to the confirmed error bit reset, and the bad byte cleared. The process is then repeated if one or more bad bytes remain in the data block.

CROSS REFERENCE

This application is related to U.S. Provisional Patent Application Ser.No. 60/390,842 filed Jun. 21, 2002.

This application is also related to co-pending U.S. patent applicationSer. Nos. PCT/______ (Atty. Docket No. IU020157), PCT/______ (Atty.Docket No. IU020158), PCT/______ (Atty. Docket No. IU020159), PCT/______(Atty. Docket No. IU020160), PCT/______ (Atty. Docket No. IU020161),PCT/______ (Atty. Docket No. IU020162), PCT/______ (Atty. Docket No.IU020252), PCT/______ (Atty. Docket No. RJ020253), PCT/______ (Atty.Docket No. IU020254), PCT/______ (Atty. Docket No. RJ020255) andPCT/______ (Atty. Docket No. IT020256), all of which were assigned tothe Assignee of the present application and hereby incorporated byreference as if reproduced in their entirety.

FIELD OF THE INVENTION

The present invention relates to error correction techniques and, moreparticularly, to a method of forward error correction of digital signalssuitable for use in broadcast routers.

BACKGROUND OF THE INVENTION

A broadcast router allows each one of a plurality of outputs therefromto be assigned the signal from any one of a plurality of inputs thereto.For example, an N×M broadcast router has N inputs and M outputs coupledtogether by a routing engine which allows any one of the N inputs to beapplied to each one of the M outputs. Oftentimes, it is desirable toconstruct a larger broadcast router, for example a 4N×4M broadcastrouter, from plural smaller broadcast routers, for example, theaforementioned N×M broadcast router. To interconnect smaller broadcastrouters requires the use of plural links, for example, copper wire, totransport signals between the smaller broadcast routers. The use of suchlinks can, however, act as a limit on the speed at which the broadcastrouter can operate.

Clock data recovery (or “CDR”) serial data links are often used whenhigh speed data transfers between devices, for example, theaforementioned broadcast routers, are desired. Heretofore, CDR serialdata links have been used in applications which allow the retransmissionof data with errors. However, when using a broadcast router, there isinsufficient time to allow for retransmissions of data As a result, inorder to use a CDR or other high speed serial data link, a broadcastrouter must be equipped for forward error correction (or “FEC”) of thereceived data. The use of current FEC techniques, for example, Viterbior Reed-Solomon FEC techniques, however, would add considerable overheadto the data transmissions. 8-bit/10-bit (or “8 B/10 B”) encoders anddecoders are often used to improve reliability in data transmissions. An8 B/10 B encoder encodes 8-bit bytes of binary data into 10-bit bytesplus a disparity bit which indicates whether there is a difference inthe number of ones and the number of zeros in the 10-bit byte.Conversely, an 8 B/10 B decoder converts 10-bit bytes of binary datainto 8-bit bytes plus a disparity bit. While 8 B/10 B encoders anddecoders can be used to identify data errors, generally, they are onlycapable of identifying data errors on a byte-wide basis and cannotidentify a particular data bit, within a “bad” data byte, which iserroneous.

SUMMARY OF THE INVENTION

The present invention is directed to an iterative method of correctingerrors in a data block. In accordance with the method, at least onesuspect bit indicative of a possible error is identified. Each suspectbit is subsequently classified as either a confirmed error bit or as anunconfirmed error bit. Each suspect bit classified as a confirmed errorbit is correct and the method repeated until all suspect bitsconfirmable as an error bit have been corrected. Preferably, theiterative method of error correction is accomplished using a combinationof information derived from 8 B/10 B encoding/decoding of the datablock, information derived from parity encoding along each row of thedata block and information derived from parity encoding along eachcolumn of the data block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a fully redundant linearly expandablebroadcast router constructed in accordance with the teachings of thepresent invention;

FIG. 2 is an expanded block diagram of a first router matrix of a firstbroadcast router component of the fully redundant linearly expandablebroadcast router of FIG. 1;

FIG. 3 an expanded block diagram of a first router matrix of a secondbroadcast router component of the fully redundant linearly expandablebroadcast router of FIG. 1;

FIG. 4 an expanded block diagram of a transmit expansion port of therouter matrix of FIG. 2 and a receive expansion port of the routermatrix of FIG. 3

FIG. 5 is a block diagram of a data block transferred between thetransmit and receive expansion ports of FIG. 4; and

FIG. 6 is a flow chart of a method of forward error correction of thedata block of FIG. 5.

DETAILED DESCRIPTION

Referring first to FIG. 1, a fully redundant linearly expandablebroadcast router 100 constructed in accordance with the teachings of thepresent invention will now be described in greater detail. As may now beseen, the fully redundant linearly expandable broadcast router 100 iscomprised of plural broadcast router components coupled to one anotherto form the larger fully redundant linearly expandable broadcast router100. Each broadcast router component is a discrete router device whichincludes first and second router matrices, the second router matrixbeing redundant of the first router matrix. Thus, each broadcast routerhas first and second routing engines, one for each of the first andsecond router matrices, each receiving, at an input side thereof, thesame input digital audio streams and placing, at an output side thereof,the same output digital audio streams. As disclosed herein, each of thebroadcast router components used to construct the fully redundantlinearly expandable broadcast router are N×M sized broadcast routers.However, it is fully contemplated that the fully redundant linearlyexpandable broadcast router 100 could instead be constructed ofbroadcast router components of different sizes relative to one another.

As further disclosed herein, the fully redundant linearly expandablebroadcast router 100 is formed by coupling together first, second, thirdand fourth broadcast router components 102, 104, 106 and 108. Of course,the present disclosure of the fully redundant linearly expandablebroadcast router 100 as being formed of four broadcast router componentsis purely by way of example. Accordingly, it should be clearlyunderstood that a fully redundant linearly expandable broadcast routerconstructed in accordance with the teachings of the present inventionmay be formed using various other numbers of broadcast routercomponents. The first, second, third and fourth broadcast routercomponents 102, 104, 106 and 108 which, when fully connected in themanner disclosed herein, collectively form the fully redundant linearlyexpandable broadcast router 100, may either be housed together in acommon chassis as illustrated in FIG. 1 or, if desired, housed inseparate chassis. While, as previously set forth, the broadcast routercomponents 102, 104, 106 and 108 may have different sizes relative toone another or, in the alternative, may all have the same N×M size, onesize that has proven suitable for the uses contemplated herein is256×256. Furthermore, a suitable configuration for the fully redundantlinear expandable broadcast router 100 would be to couple five broadcastrouter components, each sized at 256×256, thereby resulting in a1,280×1,280 broadcast router.

The first broadcast router component 102 is comprised of a first routermatrix 102 a and a second (or redundant) router matrix 102 b used toreplace the first router matrix 102 a in the event of a failure thereof.Similarly, each one of the second, third and fourth broadcast routercomponents 104, 106, and 108 of the fully redundant linearly expandablebroadcast router 100 are comprised of a first router matrix 104 a, 106 aand 108 a, respectively, and a second (or redundant) router matrix 104b, 106 b and 108 b, respectively, used to replace the first routermatrix 104 a, 106 a and 108 a, respectively, in the event of a failurethereof. Of course, the designation of the second router matrices 102 b,104 b, 106 b and 108 b as backups for the first router matrices 102 a,104 a, 106 a and 108 a, respectively, is purely arbitrary and it isfully contemplated that either one of a router matrix pair residingwithin a broadcast router component may act as a backup for the other ofthe router matrix pair residing within that broadcast router component.

As may be further seen in FIG. 1, the first router matrix 102 a of thefirst broadcast router component 102, the first router matrix 104 a ofthe second broadcast router component 104, the first router matrix 106 aof the third broadcast router component 106 and the first router matrix108 a of the fourth broadcast router component 108 are coupled togetherin a first arrangement of router matrices which conforms to a fullyconnected topology. Similarly, the second router matrix 102 b of thefirst broadcast router component 102, the second router matrix 104 b ofthe second broadcast router component 104, the second router matrix 106b of the third broadcast router component 106 and the second routermatrix 108 b of the fourth broadcast router component 108 are coupledtogether in a second arrangement which, like the first arrangement,conforms to a fully connected topology. In a fully connected topology,each router matrix of an arrangement of router matrices is coupled, by adiscrete link, to each and every other router matrix forming part of thearrangement of router matrices.

Thus, for the first arrangement of router matrices, first, second andthird bi-directional links 110, 112 and 114 couples the first routermatrix 102 a of the first broadcast router component 102 to the firstrouter matrix 104 a of the second broadcast router component 104, thefirst router matrix 106 a of the third broadcast router component 106and the first router matrix 108 a of the fourth broadcast routercomponent 108, respectively. Additionally, fourth and fifthbi-directional links 116 and 118 couple the first router matrix 104 a ofthe second broadcast router component 104 to the first router matrix 106a of the third broadcast router component 106 and the first routermatrix 108 a of the fourth broadcast router component 108, respectively.Finally, a sixth bi-directional link 120 couples the first router matrix106 a of the third broadcast router component 106 to the first routermatrix 108 a of the fourth broadcast router component 108.

Similarly, for the second arrangement of router matrices, first, secondand third bi-directional links 122, 124 and 126 couples the secondrouter matrix 102 b of the first broadcast router component 102 to thesecond router matrix 104 b of the second broadcast router component 104,the second router matrix 106 b of the third broadcast router component106 and the second router matrix 108 b of the fourth broadcast routercomponent 108, respectively. Additionally, fourth and fifthbi-directional links 128 and 130 couple the second router matrix 104 bof the second broadcast router component 104 to the second router matrix106 b of the third broadcast router component 106 and the second routermatrix 108 b of the fourth broadcast router component 108, respectively.Finally, a sixth bi-directional link 132 couples the second routermatrix 106 b of the third broadcast router component 106 to the secondrouter matrix 108 b of the fourth broadcast router component 108.

Referring next to FIG. 2, the first router matrix 102 a of the firstbroadcast router component 102 will now be described in greater detail.As may now be seen, the first router matrix 102 a of the first broadcastrouter component 102 is comprised of a routing engine 134, a transmitexpansion port 136, a first receive expansion port 138, a second receiveexpansion port 140 and a third receive expansion port 142. By the term“transmit” expansion port, it is intended to refer to an expansion portfrom which data is transmitted to a selected destination. Similarly, bythe term “receive” expansion port, it is intended to refer to anexpansion port which receives data from a destination. Residing withinthe routing engine 134 is switching means (not shown) for assigning anyone of plural input digital audio data signals received as inputs to therouting engine 134 to any one of plural output lines of the routingengine 134. Variously, it is contemplated that the routing engine 134may be embodied in software, for example, as a series of instructions;hardware, for example, as a series of logic circuits; or a combinationthereof. In a broad sense, the transmit expansion port 136 of the firstrouter matrix 102 a of the first broadcast router component 102 iscomprised of a memory subsystem (not shown) in which plural inputdigital audio data streams may be buffered before transfer to theirfinal destinations and a processor subsystem (also not shown) forcontrolling the transfer of the plural input digital audio data streamsreceived by the transmit expansion port 136 to a receive expansion portof the first router matrix of another broadcast router component.Conversely, each one of the first, second and third receive expansionports 138, 140 and 142 of the first router matrix 102 a are, in a broadsense, comprised of a memory subsystem (not shown) in which plural inputdigital audio data streams received from a transmit expansion port of afirst router matrix of another broadcast router component may bebuffered before transfer to their final destination and a processorsubsystem (also not shown) for controlling the transfer of the inputdigital audio data streams received from the receive expansion port ofthe first router matrix of the other broadcast router component toinputs of the routing engine 134.

N input digital audio data streams, each of which conforms to either theAudio Engineering Society-3 (or “AES-3”) standard or multichanneldigital audio interface (or “MADI”) standard wet forth in the AES-10standard are received by the routing engine 134 and the transmitexpansion port 136 of the first router matrix 102 a of the firstbroadcast router component 102. In this regard, it should be noted thata MADI input digital audio data stream may contains up to 32 AES-3digital audio data streams and that, if the N input digital audio datastreams input the routing engine 134 and the transmit expansion port 136conform to the MADI standard, each input digital audio data stream wouldbe a single AES-3 digital audio stream which has been previouslyextracted from a MADI input digital audio data stream by extractioncircuitry (not shown). Of course, it should be readily appreciated thatother types of input data streams other than the input digital audiostreams disclosed herein are equally suitable for use with the firstrouter matrix 102 a of the first broadcast router component 102. Forexample, it is contemplated that the first router matrix 102 a of thefirst broadcast router component 102 may instead be used with other lowbandwidth digital signals such as compressed video and data signals. Itis further contemplated that, with minor modifications, for example,faster hardware, the first router matrix 102 a of the first broadcastrouter component 102 may be used with non-compressed digital videosignals.

Referring next to FIG. 3, the first router matrix 104 a of the secondbroadcast router component 104 will now be described in greater detail.As may now be seen, the first router matrix 104 a of the secondbroadcast router component 104 is comprised of a routing engine 144, atransmit expansion port 146, a first receive expansion port 148, asecond receive expansion port 150 and a third receive expansion port152. Residing within the routing engine 144 is switching means (notshown) for assigning any one of plural input digital audio data signalsreceived as inputs to the routing engine 144 to any one of plural outputlines of the routing engine 144. Variously, it is contemplated that therouting engine 144 may be embodied in software, for example, as a seriesof instructions; hardware, for example, as a series of logic circuits;or a combination thereof. In a broad sense, the transmit expansion port146 of the first router matrix 102 a is comprised of a memory subsystem(not shown) in which plural input digital audio data streams may bebuffered before transfer to their final destinations and a processorsubsystem (also not shown) for controlling the transfer of the pluralinput digital audio data streams received by the transmit expansion port146 to a receive expansion port of the first router matrix of anotherbroadcast router component. Conversely, each one of the first, secondand third receive expansion ports 148, 150 and 152 of the first routermatrix 104 a of the second broadcast router component 104 are, in abroad sense, comprised of a memory subsystem (not shown) in which pluralinput digital audio data streams received from an expansion port of afirst router matrix of another broadcast router component may bebuffered before transfer to their final destination and a processorsubsystem (also not shown) for controlling the transfer of the inputdigital audio data streams received from the receive expansion port ofthe first router matrix of the other broadcast router component toinputs of the routing engine 144.

Input digital audio data streams 1 through N are fed into the routingengine 134 and the transmit expansion port 136 of the first routermatrix 102 a of the first broadcast router component 102. From thetransmit expansion port 136, input digital audio data streams 1 throughN are forwarded to the first receive expansion port 148 of the firstrouter matrix 104 a of the second broadcast router component 104, areceive expansion port (not shown) of the first router matrix 106 a ofthe third broadcast router component 106 and a receive expansion port(also not shown) of the fourth router matrix 108 a of the fourthbroadcast router component 108. In turn, input digital audio datastreams N+1 through 2N, 2N+1 through 3N and 3N+1 through 4N aretransmitted, by the transmit expansion port of the first router matrixof the second, third and fourth broadcast router components 104, 106 and108, respectively, to the first, second and third expansion ports 138,140 and 142, respectively, of the first router matrix 102 a of the firstbroadcast router component 102.

Similarly, input digital audio data streams N+1 through 2N are fed intothe routing engine 144 and the transmit expansion port 146 of the firstrouter matrix 104 a of the second broadcast router component 104. Fromthe transmit expansion port 146, input digital audio data streams N+1through 2N are forwarded to the first receive expansion port of thefirst router matrix 102 a of the first broadcast router component 102, areceive expansion port (not shown) of the first router matrix 106 a ofthe third broadcast router component 106 and a receive expansion port(also not shown) of the fourth router matrix 108 a of the fourthbroadcast router component 108. In turn, input digital audio datastreams 1 through N, 2N+1 through 3N and 3N+1 through 4N aretransmitted, by the transmit expansion port 136 of the first routermatrix 102 a of the first broadcast router component, a transmitexpansion port (not shown) of the first router matrix 106 a of the thirdbroadcast router component 106 and a transmit expansion port (also notshown) of the first router matrix 108 a of the fourth broadcast routercomponent 108, respectively, to the first, second and third expansionports 148, 150 and 152, respectively, of the first router matrix 104 aof the second broadcast router component 104.

Referring next to FIG. 4, the transfer of input digital audio datastreams 1 through N from the transmit expansion port 136 of the firstrouter matrix 102 a of the first broadcast router component 102 to thereceive expansion port 148 of the first router matrix 104 a of thesecond broadcast router component 104 along the link 110 will now bedescribed in greater detail. While, as disclosed herein, 8 B/10 Bencoding/decoding is applied to the input digital audio data streams 1through N, it should be clearly understood that other encoding/decodingschemes may be used instead. For example, it is fully contemplated thata 4-bit/5-bit (or “4 B/5 B”) encoder and decoder may be used in place ofthe 8 B/10 B encoder and decoder disclosed herein. Finally, in additionto 4 B/5 B encoding/decoding, it is further contemplated that encodersand decoders which employ other encoding/decoding schemes similar to 8B/10 B encoding/decoding would be suitable as well.

As will be more fully described below, upon initiation of the transferof the input audio data streams 1 through N from the transmit expansionport 136 to the first receive port 148, the data streams are forwardedfrom the memory subsystem forming part of the transmit expansion port136 to a parity encoder 154 also forming part of the transmit expansionport 136. At the parity encoder 154, the input audio data streams 1through N undergo parity encoding along both the horizontal and verticalaxes. From the parity encoder 154, the parity encoded data streams 1through N are then forwarded to an 8 B/10 B encoder 156 for 8 B/10 Bencoding. From the 8 B/10 B encoder 156, the 8 B/10 B parity encodeddata streams are then transferred to the first receive expansion port148 over the link 110. Upon receipt by the first receive expansion port148, the 8 B/10 B parity encoded data streams 1 through N are forwardedto an 8 B/10 B decoder 158. From the received 8 B/10 B parity encodeddata streams, the 8 B/10 B decoder 158 generates parity encoded datastreams 1 through N and byte error detect information which indicateswhich data bytes of the parity encoded data streams 1 through N are“bad” data bytes containing one or more erroneous bits of data.

From the 8 B/10 B decoder 158, the parity encoded data streams 1 throughN are forwarded to both an FEC circuit 160 and a parity decoder 162.Additionally, the 8 B/10 B decoder 158 forwards byte error detectinformation to the FEC circuit 160. By decoding the received parityencoded data streams 1 through N, the parity decoder 162 generates biterror information for subsequent forwarding to the FEC circuit 160.Using the byte error detect information received from the 8 B/10 Bdecoder 158 in combination with the bit error information received fromthe parity decoder 162, the FEC circuit 160 executes an iterativealgorithm described below with respect to FIG. 6 to correct those errorscontained in the parity encoded data streams. Once the errors in theparity encoded data streams are corrected by the FEC circuit 160, theerror corrected, parity encoded data streams 1 through N are forwardedto the memory subsystem of the first receive expansion port 148 forfurther handling in the manner previously described. Of course, sincethe data streams 1 through N have already been corrected for parityerrors, parity information contained in the data streams 1 through N mayeither be dropped by the FEC circuit 160 prior to transmission of thedata streams 1 through N to the memory subsystem of the first receiveexpansion port 148 or carried forward with the data streams 1 through Nto the memory subsystem of the first receive expansion port 148 butsubsequently ignored thereat.

Referring next to FIG. 5, a block 164 of parity encoded data produced bythe parity encoder 154 will now be described in greater detail. As maynow be seen, each data block 164 is comprised of X bytes of the inputdigital audio data streams 1 through N. Each input digital audio datastream forms a row of the data block 164 while each bit of each byteforms a column of the data block 164. For each input 1 through N, theparity encoder 154 constructs a parity byte comprised of parity bits 0through 7. For example, parity byte 166 is constructed for input digitalaudio data stream 0. Bit 0 of the parity byte 166 is calculated bysumming all of the bit 0's for bytes 1 through X of input digital audiodata stream 0. In other words, bit 0 of the parity byte 166 iscalculated by summing all of the bit 0's in row 167 of the data block164. Bits 1 through 7 of the parity byte 166 ate similarly calculated.The data block further includes a parity frame 168 having X+1 bytes.Each bit of the parity frame 168 is calculated, by the parity encoder154, by summing the same bit for each one of the 1 through N input datastreams. In other words, a bit of the parity frame 168 is calculated bysumming all of the bits in a column of the data block 164. For example,bit 169 of the parity frame 168 is calculated by summing all of the bitsin row 171 of the data block 164. While a parity frame may be calculatedfor any number of rows, calculating a parity frame for every 32 inputdata streams has been suitable for the uses contemplated herein.

Referring next to FIG. 6, a method of forward error correction of a datablock, for example, the data block 164 of FIG. 5, by the FEC circuit 160will now be described in greater detail. It should be clearlyunderstood, however, that while the disclosed technique is describedwith respect to a data block transmitted between components of abroadcast router, it is fully contemplated that the technique is equallyapplicable for use with data blocks transmitted between other types ofdevices. The method commences at step 170 with the parity decoder 162receiving the data block 164 from the 8 B/10 decoder 158 and the FECcircuit 160 receiving both the data block 164 and byte-error detectinformation from the 8 B/10 B decoder 158. At step 171, the paritydecoder 162 decodes the received data block 164 to generate potentialbad bit information for the received data block 164 and forwards thegenerated potential bad bit information to the FEC circuit 160. Togenerate a first component of the potential bad bit information for thereceived data block, the parity decoder performs a bit-by-bit check ofthe parity byte for each row of the data block 164. To do so, the paritydecoder 162 selects a row of the data block 164, sums bit 0 for bytes 1through X of the selected row and then compares the calculated sum tobit 0 of the parity byte for the selected row. If the two fail to match,the parity decoder 162 identifies bit 0 of each byte of the selected rowas a suspect bit. The parity decoder 162 would then perform similardeterminations for bits 0 through 7 of the selected row. By doing so,all suspect bits for each data byte of the selected row are identified.The process would then be repeated for each row of the data block 164.For example, if row 167 and bit 0 were selected for checking, the paritydecoder 162 would sum bit 0 for bytes 0 through X for comparison to bit0 of the parity byte 166 for the row 167. If the determined sum of bit 0of bytes 0 through X of the row 167 does not agree with the value of bit0 of the byte 166, the parity decoder 162 would determine that bit 0 ofeach one of bytes 0 through X of row 167 is a potential bad bit.

To generate a second component of the potential bad bit information forthe received data block 164, the parity decoder 162 performs abit-by-bit check on the parity frame. To do so, the parity decoderselects a column of the data block 164, sums the data bit contained inthe selected column for inputs 1 through N and then compares thecalculated sum to the bit of the parity frame contained in the selectedcolumn. If the two fail to match, the parity decoder 162 determines thatthe selected column contains a bad bit and identifies, for each one ofinputs 1 through N, the bit contained in the selected column as asuspect bit. The process would then be repeated for each column of thedata block 164. For example, if the column corresponding to bit 3 ofbyte 1 were selected, the parity decoder 162 would sum bit 3 of byte 1for inputs 1 through N for comparison to bit 3 of byte 1 of the parityframe 168. If the determined sum of bit 3 of byte 1 for inputs 1 throughN does not agree with the value of bit 3 of byte 1 of the parity frame168, then the parity decoder 162 would determine that bit 3 of byte 1 ofeach input 1 through N is a potentially bad bit.

Proceeding on to step 172, the FEC circuit 160 checks the received byteerror detect information to see if the received data block 164 containsone or more bad bytes. A bad byte is identified whenever a check of thereceived byte error detect information produces a decoding error (thereceived code is not a legal value) or an anomaly (the received code isa legal value but has a disparity problem). As previously discussed, 8B/10 B decoding is capable of identifying whether any particular byte ofdata is bad but cannot identify which bits of the data byte is causingit to be bad. For example, the byte error detect information mayindicate that byte 1 of input 0 and byte 3 of input 2 are bad. If it isdetermined at step 172 that the byte error detect information indicatesthat the data block 164 does not contain any bad bytes, the method endsat step 174. If, however, it is determined at step 172 that the datablock 164 contains one or more bad bytes, the method proceeds to step176.

A first row of the data block 164, for example, the row 167corresponding to input 0, is selected at step 176 and, at step 178, theFEC circuit 160 determines, from the byte error detect information, ifthere is one or more bad byte in the selected row. If there are no badbytes in the selected, row, the method proceeds to step 180 where a nextrow, for example, the row corresponding to input 1 is selected and thenreturns to step 178 for further processing in the manner describedherein. If, however, the FEC circuit 160 determines, at step 178, thatthe selected row contains one or more bad bytes, the method will insteadproceed to step 182 where a first bad byte of the selected row, forexample, byte 1 of row 0 is selected for further processing. At step 184the FEC circuit 160 checks the selected bad for the selected row todetermine if there are any suspect bits for the selected bad byte. To doso, the FEC circuit 160 checks the first component of the potential badbit information supplied by the parity decoder 162 to see if a suspectbit was identified for the selected bad byte.

If a review of the first component of the potential bad bit informationsupplied by the parity decoder indicates that none of the bits of theselected bad byte are suspect, the FEC circuit 160 determines that theselected bad byte is no longer bad. Accordingly, the method will proceedto step 186 where the selected bad byte is “cleared”, typically, byremoving the bad byte from the list of bad bytes contained in the byteerror detect information received, by the FEC circuit 160, from the 8B/10 B decoder 158. After clearing the selected bad byte at step 186,the method will proceed to step 208, below, for further processing. If,however, a review of the first component of the potential bad bitinformation supplied by the parity decoder indicates that one or more ofthe bits of the selected bad byte are suspect, the method will insteadproceed to step 188 for selection of a first suspect bit of the selectedbad byte.

Continuing on to step 190, the FEC circuit 160 then reviews the secondcomponent of the potential bad bit information to determine if there isthe suspect bit is located in a column of the data block 164 previouslydetermined as containing a bad bit. For example, if bit 3 of byte 1 forinput 0 is the selected suspect bit, at step 190, the FEC circuit 160would check the second component of the potential bad bit information tosee if the suspect bit is located in a column previously determined tocontain a bad bit. If the FEC circuit 160 determines that the suspectbit is not located in a column previously determined to contain a badbit, the method would first proceed to step 192 where the FEC circuit160 would conclude that the suspect bit is correct and then on to step194 where it is determined if there are additional suspect bits in theselected bad byte requiring examination.

If, however, it is determined at step 190 that the suspect bit islocated in a column identified, by the second component of the potentialbad bit information, as containing a bad bit, the method will insteadproceed to step 196 where the first component of the potential bad bitinformation is reviewed to determine if any of the unselected rows theunselected rows where the bit position of the parity byte whichcorresponds to the suspect bit is checked for the unselected rows. Forexample, if bit 3 of byte 1 for input 0 is the selected suspect bit andit is determined from the review of the second component of potentialbad bit information that there is an error in bit 3 of byte 1 for one ofthe input 1 through N, the FEC circuit 160 will review the contents ofthe first component of the potential bad bit information to see if bit 3of byte 1 for any of inputs 1 through N where identified as suspect.Proceeding on to step 198, if a review of the first component of thepotential bad bit information reveals that that none of the bits in theunselected rows which correspond to the suspect bit are themselvessuspect, then the FEC circuit 160 concludes that the suspect bit iserroneous. The method will then proceed to step 200 where the FECcircuit 160 corrects the suspect bit.

If, however, it is determined at step 198 that the bit in one or more ofthe unselected rows which corresponds to the suspect bit is suspectitself, the method will instead proceed to step 204 where the FECcircuit 160 concludes that the selected suspect bit remains suspect andcannot be corrected at this time. Upon either: (1) concluding, at step192, that the suspect bit is correct; (2) correcting the selectedsuspect bit at step 200; or (3) concluding, at step 204, that theselected suspect bit must remain suspect, the method proceeds to step194 where the FEC circuit 160 determines if there are additional suspectbits in the selected bad byte. If it is determined at step 194 thatthere are additional suspect bits in the selected bad byte, the methodwill proceed to step 206 for selection of a next suspect bit of theselected bad byte. The method will then return to step 190 forprocessing of the newly selected suspect bit in the manner previouslydescribed.

If, however, it is determined at step 194 that there are no additionalsuspect bits in the selected bad byte, the method will instead proceedto step 208 where the FEC circuit 160 determines if there are additionalbad bytes in the selected row, again by checking the list of bad bytesprovided as part of the byte error detect information received from the8 B/10 B decoder 158. If the check of the list of bad bytes indicatesthat there are one or more additional bad bytes in the selected row, themethod will proceed to step 210 for selection of a next bad byte in theselected row. The method will then return to step 184 for furtherprocessing of the newly selected bad byte in the manner previouslydescribed. If, however, it is determined at step 208 that there are noadditional bad bytes in the selected row, the method will insteadproceed to step 212 where it is determined if there are additional rowsin the data block 164 to be examined. If it is determined at step 212that there are additional rows in the data block 164 to be examined, the25 method will proceed to step 214 for selection of a next row of thedata block 164. The method will then return to step 178 for furtherprocessing in the manner previously described. If, however, it isdetermined at step 212 that there are no additional rows to be examined,in other words, each one of the rows 1 through N have been examined, themethod will return to step 172 for further processing in the mannerpreviously described.

The foregoing process is an iterative method of correcting errorscontained in a data block such as the data block 176. In each passthrough steps 170 through 214, plural suspect bits are typicallyidentified for the data block 176. However, not all of the suspect bitswill be confirmed as error bits. Some will remain suspect because thereare plural bits in a column which are suspect. However, each time thatan error bit is corrected, it is increasingly likely that a subsequentpass will clear a bit which had remained as a suspect bit. Thus, it isexpected that each iterations of steps 170 through 214 has the potentialto identify and correct additional error bits until, ideally, all errorbits have been corrected and all bad bytes have been cleared. In oneaspect, the number of iterations of the process to be performed may bepreselected. For example, testing has revealed that a high percentage oferrors are corrected after two iterations. In another aspect, a maximumnumber of iterations may be preselected and the process configured toterminate upon either executing the maximum number of iterations orwhere repeated iterations are not improving the condition of the datablocks. For example, a count of suspect bits and/or bad bytes may bemaintained and the process terminated if one or more iterations areperformed but the count of suspect bits and/or bad bytes has not beenreduced. In the alternative, the number of corrected bad bytes could bemaintained and the process terminated upon correction of a pre-selectedpercentage of the original number of bad bytes in the data block.

Thus, there has been disclosed and illustrated herein, a method offorward error correction of digital signals which is suitable for use inbroadcast routers. It should be clearly understood, however, that whilepreferred embodiments of this invention have been shown and describedherein, various modifications and other changes can be made by oneskilled in the art to which the invention pertains without departingfrom the spirit or teaching of this invention. Accordingly, the scope ofprotection is not limited to the embodiments described herein, but isonly limited by the claims that follow.

1. A method of correcting errors in a data block having N rows and Xcolumns, comprising: performing a parity check for each one of said Nrows of said data block; performing a parity check for each one of saidX columns of said data block; identifying at least one bad byte for saiddata block; identifying, from said parity check for each one of said Nrows of said data block said check for each one of said X columns ofsaid data block and said at least one identified bad bytes for said datablock, at least one error in said data block; and correcting each one ofsaid at least one identified error in said data block.
 2. The method ofclaim 1, wherein said at least one bad byte for said data block isidentified using an 8 B/10 B encoding/decoding process.
 3. The method ofclaim 2, wherein N equals
 32. 4. The method of claim 1, wherein each oneof said at least one identified bad byte is located in one of said Nrows of said data block.
 5. The method of claim 4, wherein identifyingat least one error in said data block further comprises: identifying atleast one suspect bit for each one of said at least one bad byte of saiddata block, each one of said at least one identified suspect bit beinglocated in one of said X columns of said data block; and determining,for each one of said at least one suspect bit, if a parity bit for acorresponding one of said X columns of said data block confirms thatsaid suspect bit is suspect.
 6. The method of claim 5, whereincorrecting each one of said at least one identified error in said datablock further comprises: for each confirmed suspect bit, determining ifat least one additional bit in said corresponding one of said X columnsof said data block is also suspect; and if no other bit in saidcorresponding one of said X columns of said data block is also suspect,correcting said confirmed suspect bit.
 7. The method of claim 4, andfurther comprising identifying at least one suspect bit for each one ofsaid at least one bad byte of said data block, each one of said at leastone identified suspect bit being located in one of said X columns ofsaid data block.
 8. The method of claim 7, wherein identifying at leastone suspect bit for each one of said at least one bad byte for said datablock further comprises: performing a parity check for each row of saiddata block in which one or more of said at least one bad byte islocated; and identifying suspect bits for each said parity checked row;wherein said identified suspect bits for said parity checked row aresaid identified suspect bits for said bad byte.
 9. The method of claim8, wherein identifying at least one error in said data block furthercomprises: identifying at least one suspect bit for each one of said atleast one bad byte of said data block, each one of said at least oneidentified suspect bit being located in one of said X columns of saiddata block; and determining, for each one of said at least one suspectbit, if a parity bit for a corresponding one of said X columns of saiddata block confirms that said suspect bit is suspect.
 10. The method ofclaim 9, wherein correcting each one of said at least one identifiederror in said data block further comprises: for each confirmed suspectbit, determining if at least one additional bit in said correspondingone of said X columns of said data block is also suspect; and if noother bit in said corresponding one of said X columns of said data blockis also suspect, correcting said confirmed suspect bit.
 11. The methodof claim 10, and further comprising: for each said corrected suspectbit, correcting said suspect bit of said parity byte for a correspondingrow of said data block.
 12. A method of correcting errors in a datablock, comprising: (a) identifying at least one suspect bit in said datablock, each one of said at least one suspect bit indicating a possibleerror in said data block; (b) classifying each one of said at least onesuspect bit as either a confirmed error bit or as an unconfirmed errorbit; and (c) correcting each one of said at least one suspect bitclassified as a confirmed error bit.
 13. The method of claim 12, andfurther comprising: (d) repeating (a) through (c) until all errors insaid data block have been corrected.
 14. The method of claim 12, whereinsaid confirmed error bits are identified using a combination ofinformation derived from 8 B/10 B encoding/decoding of said data block,information derived from parity encoding along each row of said datablock and information derived from parity encoding along each column ofsaid data block.
 15. The method of claim 14, wherein identifying atleast one suspect bit of said data block further comprises identifyingat least one bad byte of said data block using information derived fromsaid 8 B/10 B encoding/decoding of said data block.
 16. The method ofclaim 15, wherein classifying each one of said at least one suspect bitas either a confirmed error bit or as an unconfirmed error bit furthercomprises: identifying, using information derived from parity encodingof a row of said data block in which a first one of said at least onebad byte is located, at least one suspect bit for said first one of saidat least one bad byte.
 17. The method of claim 16, wherein a first oneof said at least one suspect bit for said first one of said at least onebad byte is classified as either a confirmed error bit or as anunconfirmed error bit using information derived from parity encoding ofa column of said data block in said first suspect bit is located. 18.The method of claim 12, and further comprising the steps of: applying apre-selected number of iterations of an error-correction routine to saiddata block; said error-correction routine being comprised of (a), (b)and (c).
 19. The method of claim 18, wherein said pre-selected number istwo.
 20. The method of claim 19, wherein said confirmed error bits areidentified using a combination of information derived from 8 B/10 Bencoding/decoding of said data block, information derived from parityencoding along each row of said data block and information derived fromparity encoding along each column of said data block.
 21. The method ofclaim 20, wherein identifying at least one suspect bit of said datablock further comprises identifying at least one bad byte of said datablock using information derived from said 8 B/10 B encoding/decoding ofsaid data block A.
 22. The method of claim 21, wherein classifying eachone of said at least one suspect bit as either a confirmed error bit oras an unconfirmed error bit further comprises: identifying, usinginformation derived from parity encoding of a row of said data block inwhich a first one of said at least one bad byte is located, at least onesuspect bit for said first one of said at least one bad byte.
 23. Themethod of claim 22, wherein a first one of said at least one suspect bitfor said first one of said at least one bad byte is classified as eithera confirmed error bit or as an unconfirmed error bit using informationderived from parity encoding of a column of said data block said firstsuspect bit is located.